(1) Field of the Invention
The invention relate s to processes for the manufacture of semiconductor devices and more particularly to processes for forming self-aligned polysilicon gate field effect transistors.
(2) Description of Prior Art and Background to the Invention
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation n-channel FETs(NMOS) and p-channel FETs(PMOS) in combination to form low current, high performance integrated circuits. The complimentary use of NMOS and PMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
The basic MOSFET, whether it be NMOS or PMOS is typically formed by a self-aligned polysilicon gate process. Referring to FIG. 1, there is shown a cross section of a wafer 10 illustrating the formation of an n-channel MOSFET. Field oxide isolation(FOX) regions 12 are formed on a p-type silicon wafer 10 by the well known process of local oxidation of silicon(LOCOS).
A gate oxide 14 is grown in the exposed silicon regions and a polysilicon layer 16 is deposited over it by low pressure chemical vapor deposition(LPCVD). The polysilicon layer 16 is typically undoped. A second conductive layer 18 comprising a transition metal silicide, for example WSi.sub.x, is deposited over the polysilicon layer 16. The term polycide is commonly used to denote the silicide over polysilicon combination. The polysilicon layer 16 may itself be comprised of a lower undoped region and an upper doped region to make it more conductive. The second conductive layer 18 is applied to increase the conductivity of the gate electrode which will subsequently be formed. A photoresist layer 20 is deposited over the second layer 18 and patterned by photolithography to define a gate electrode which is then formed by etching the second conductive layer 18 and the polysilicon layer 16 by an anisotropic plasma etching technique, for example reactive ion etching (RIE).
Referring to FIG. 2, the layers are etched down to the gate oxide 14, thereby forming the gate electrode 22. The sequence of layers which form the gate electrode are referred to as the gate stack 21. The etchants used are selected to provide a high polysilicon-to-silicon oxide selectivity so that the gate oxide layer functions as an etch stop and further permits an over etch period wherein residual pockets of polysilicon are removed.
Referring now to FIG. 3, the residual photoresist 20 is stripped and lightly doped drain (LDD) regions 24 are formed by ion implantation of a dopant species, for example arsenic. The LDD implantation step is shown in the cross section of FIG. 3. The regions 24 are self-aligned to the polysilicon gate.
Anisotropic etching of the two layer gate stack 21 is conventionally accomplished by RIE or anisotropic plasma etching using etchants containing chlorine, for example Cl.sub.2, or CCl.sub.4. The etching of the two layers is performed in a single operation in an RIE reactor by first etching upper layer 18 with a first combination of reactants and conditions and then etching the lower layer 16 with a second combination. The lower polysilicon layer 16 is sometimes etched in two steps, the first, having a low polysilicon/oxide selectivity for removing the bulk of the layer and the second having a high polysilicon/oxide selectivity in order to avoid excessive penetration of the thin underlying gate oxide. A high selectivity also permits an over-etch period which is necessary to assure the removal of any residual pockets of polysilicon.
The balance between the thorough removal of polysilicon in the exposed regions and the avoidance of gate oxide penetration becomes increasingly delicate as the gate oxide becomes thinner. The probability of local penetration often caused by thin spots or other defects in the gate stack increases rapidly as gate oxide thicknesses fall below about 125 .ANG.. Once local penetration is achieved, the underlying single crystalline silicon is rapidly attacked and becomes deeply pitted by the silicon etchant. The high selectivity of the final etch step now becomes a liability instead of an asset.
FIG. 4 is a cross section of a gate stack after etching showing deep pits or trenches 30 in the silicon where the polysilicon etchant has penetrated the thin gate oxide layer and etched the underlying silicon. The pits 30 occur mostly near the edge of the gate stack but are found in other regions as well. FIG. 5 is a plan view showing the typical location and shape of the pits adjacent to the gate electrode 22. The cross section of FIG. 4 is represented by the line 4--4'. The severity of the pitting can be related to the amount of polysilicon over etch. However, if the over etch period is reduced to abate the pitting, isolated pockets of polysilicon remain. This dilemma is resolved by the current invention by eliminating a major cause of the development of thin spots in the gate stack.
The current invention teaches that the ultimate cause of the pitting of the silicon is a native oxide layer which forms on the surface of the uppermost layer 18 prior to etching. In etching the gate stack, the polysilicon etchant must first break through the native oxide layer in order to attack the polycide layer 18. Because the native oxide is very thin and highly resistive to the polysilicon etchant, the breakthrough is uneven and occurs first in isolated spots forming pits which are then propagated down through the silicide and polysilicon layers to the gate oxide. Gate oxides less than 125 .ANG. thick are incapable of absorbing these irregularities and are consequently penetrated by the polysilicon etch.
In a frequently used variation of gate electrode formation, a three layer gate stack is employed. A cross section of such a gate stack is shown in FIG. 6. The third layer 26 is formed of an insulative material, for example silicon oxide. The insulator 26 prevents shorting of subsequently formed contact metallurgy to the gate electrode. The three layer gate stack is of particular benefit in the formation of self-aligned contacts.
A conventional method for etching the three layer gate stack involves the use of two separate RIE reactors. The oxide layer 26 is etched in a first RIE reactor which is dedicated to oxide etching. The wafer is then transferred to a second reactor configured for silicon etching wherein the polycide layers are etched. This practice is often convenient and practical because the configuration of oxide etching tools and silicon etching tools require different cathode materials for optimum etch rate selectivities.
In a variation of the three stack process, the oxide layer 26 is used as a hardmask for etching the subjacent polycide gate stack and is first patterned by photoresist. The photoresist is then stripped and the polycide gate stack is etched. In yet another variation the oxide layer 26 may be applied thinner(0.1 to 0.2 microns) than that in the conventional three layer stack, used only as a hardmask, and removed after the gate stack silicon etch.
Because the suicide layer 18 is exposed to atmosphere during the transfer from the oxide etching reactor to the silicon etching reactor, a native oxide is formed on the exposed polycide. Consequently, the problem of pitting or trenching of the underlying silicon caused by the penetration of thin gate oxides (&lt;125 .ANG.) is also observed in a three layer gate stack formed by the two reactor process.
Efforts to combine the silicon etching and oxide etching into a one tool single pumpdown operation for etching of the three layer gate stack have been proposed. This significantly reduces the chance of native oxide formation on the polysilicon after the oxide has been removed. However, these methods have other drawbacks which make them unsuitable for use in etching gate stacks with ultra thin gate oxides.
Long, et.al., U.S. Pat. No. 5,013,398 provides a method wherein both the oxide and polycide etches are accomplished in a single tool with a single non-erodible cathode. The oxide etch, which normally prefers an erodible electrode, is done in two stages with SF.sub.6 and CHF.sub.3 in a helium carrier gas. SF.sub.6, typically a silicon etchant is added in small quantity and in critical measure to the CHF.sub.3.
The convenience of single tool etching process invariably has it's trade-offs. Because a non-erodible cathode is used, it is difficult to achieve the high oxide/polysilicon selectivities affordable in a dedicated oxide etcher with an erodible cathode. In addition, it is difficult to time the endpoint of the oxide etch with sufficient accuracy and the over etch period required to clear all the oxide is longer than the period that would be required to etch a native oxide only. This leads to penetration of regions of polysilicon where the oxide clears early during the oxide overetch step. Thickness variations in the oxide are therefore translated into the polysilicon, whereas under high selectivity conditions, they would be eliminated. These irregularities are then added to any polysilicon thickness irregularities thereby extending the amount of polysilicon overetch necessary to completely clear the subjacent gate oxide. Clearly, extending the polysilicon overetch period over ultra thin gate oxides is not a favorable approach.
Becker, et. al., U.S. Pat. No. 5,094,712 cites the use of a magnetically enhanced RIE etcher used in a plasma etch mode. The oxide etch is CF.sub.4 /CHF.sub.3 and a selectivity of oxide to WS.sub.ix of about 7.5:1 is cited. Langley, U.S. Pat. No. 5,201,993 reports high pressure (2-4 Torr) etching of the oxide layer in a single electrode system using C.sub.2 F.sub.6 which provides more CFx etchant species and fewer fluorine radicals, resulting in an improved oxide/silicon selectivity. However, drawbacks of the high pressure method include photoresist damage and increased sidewall etching.